About Anti-Tamper Digital Clocks
About Anti-Tamper Digital Clocks
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usually means for evaluating that employs the plurality of delayed monotone alerts to detect a voltage fault and
The reset time period can be just before the Consider time frame. Using the clock to result in the Examine circuit might utilize a clock edge at an conclusion of the Examine time frame to trigger the Examine circuit.
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26. The strategy for detecting voltage tampering as defined in claim 23, wherein the evaluate circuit decides regardless of whether the number of ones from the plurality of delayed monotone signals differs from a drinking water level selection by a lot more than a predetermined threshold.
implies for delaying the monotone signal to crank out a plurality of delayed monotone alerts acquiring discretely escalating hold off times in between a least delay time and also a optimum hold off time and each in the plurality of delayed monotone alerts having both a a person or maybe a zero logic benefit;
With further reference to FIG. seven, An additional element of the invention may perhaps reside within an equipment for detecting clock tampering, comprising: a first circuit 750A, a first plurality of resettable hold off line segments 710, a 2nd circuit 750B, a 2nd plurality of resettable delay line segments 720, and an Consider circuit 240. The main circuit supplies a first monotone signal for the duration of a primary clock Appraise time period affiliated with a clock. The first plurality of resettable hold off line segments each delay the main monotone sign to produce a respective initial plurality of delayed monotone alerts. Resettable hold off line segments amongst a resettable delay line section associated with a least delay time and also a resettable hold off line segment associated with a utmost hold off time are Just about every connected to discretely growing hold off situations. The second circuit supplies a second monotone signal for the duration of a next clock Consider time period associated with the clock.
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nine. The equipment for detecting clock tampering as described in assert eight, even more comprising: suggests for resetting the usually means for delaying the monotone get more info sign during a reset period of time, wherein the reset period of time is before the clock Examine period of time.
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27. The tactic for detecting voltage tampering as defined in assert 26, wherein the water stage amount is determined depending on delayed monotone signals from a number of earlier Examine time.
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